- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Austin, TX)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Austin, TX)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Microsoft Corporation (Redmond, WA)
- … verification plans, develop SystemVerilog testbenches using Universal Verification Methodology ( UVM ), and collaborate closely with firmware, software, ... that shape the future for millions worldwide. As a Design Verification Engineer in Azure Core, you...technical leadership, mentor engineers, and deepen your expertise in UVM . As part of a focused verification … more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Boise, ID)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Capgemini (Seattle, WA)
- …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
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