- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Menlo Park, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Menlo Park, CA)
- … verification 8. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Menlo Park, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with… more
- Meta (Austin, TX)
- … UVM methodology 10. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...or a related field 18. Experience in development of UVM based verification environments from scratch 19.… more
- Northrop Grumman (Mcclellan, CA)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Google (Mountain View, CA)
- …+ 1 year of experience with verifying digital logic at RTL using SystemVerilog or Universal Verification Methodology ( UVM ). Preferred qualifications: + ... verification scenarios. + Enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ), or… more
- Amazon (Boise, ID)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Qualcomm (San Diego, CA)
- … design team. + Architect and develop the testbench using advanced verification methodology such as SystemVerilog / UVM , Analog/mixed signal simulation, Low ... Group, Engineering Group > ASICS Engineering **General Summary:** Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP… more
Recent Jobs
-
Sr. Staff Global Supplier Quality Engineer - Metals
- Beckman Coulter Diagnostics (Miami, FL)
-
Manufacturing Design Transfer Engineer
- Cytiva (Miami, FL)
-
Sr. Business Intelligence Engineer, Advertising Identity
- Amazon (Palo Alto, CA)
-
Quality Assurance Engineer
- Cytiva (Muskegon, MI)