- US Tech Solutions (Goleta, CA)
- …AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer , you will own functional ... and testing. **Mandatory:** + 8 years of experience with verification methodologies and languages such as UVM ...with verification methodologies and languages such as UVM and SystemVerilog. + Experience developing and maintaining … more
- US Tech Solutions (Goleta, CA)
- …and GLS bringup and testing **Experience:** + 6+ years of experience with verification methodologies and languages such as UVM and SystemVerilog. + Experience ... Experience in analog and real number modeling preferred **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG + SDF and GLS… more
- Amazon (Redmond, WA)
- …networking and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating & Maintaining ...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based… more
- Skyworks (Cedar Rapids, IA)
- Sr. Verification Engineer Apply now " Date:May...expected and verify model accuracy + Write System Verilog UVM testbench code for die level verification ... ID: 75221 Description If you are a Mixed Signal Verification engineer with 4+ years of experience,... UVM libraries + 2+ years experience writing UVM testbenches for mixed signal verification +… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Actalent (Redmond, WA)
- Job Title: Silicon Verification Engineer Job Description The Silicon Verification Engineer plays a crucial role in the test-plan generation process, ... field of AI technology. Responsibilities + Define, document, and implement a UVM verification environment, including agents and scoreboards. + Write test… more
- Northrop Grumman (Linthicum Heights, MD)
- …career. We are looking for you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification Engineer based out of ... This requisition may be filled as a Principal Digital Engineer or a Senior Principal Digital Engineer ....complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. +… more
- SpaceX (Redmond, WA)
- Design Verification Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
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