• Senior VLSI Physical Design…

    NVIDIA (Westford, MA)
    …work, to amplify human inventiveness and intelligence. NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated ... a significant impact! What you'll be doing: + Run integration flows to build RTL, run connectivity checks, and...equivalent experience. + Minimum 5+ years of experience in VLSI physical design implementation on… more
    NVIDIA (06/30/25)
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  • VLSI Physical Design…

    NVIDIA (Westford, MA)
    …life's work, to amplify human inventiveness and intelligence. NVIDIA is seeking an outstanding VLSI Physical Design Integration Engineer who is dedicated ... a significant impact! What you'll be doing: + Run integration flows to build RTL, run connectivity checks, and...to ensure physically-viable RTL netlists are delivered to downstream physical design flows. + Project level cell… more
    NVIDIA (05/07/25)
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  • Principal Engineer, VLSI Design…

    SanDisk (Milpitas, CA)
    … and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration , synthesis, DFT, timing analysis and closure + Balance ... Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a...years of relevant experience + Experience with chip level integration , chip lead, and full product life cycle (requirements,… more
    SanDisk (07/17/25)
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  • Entry Level Logic Design Engineer…

    IBM (Rochester, MN)
    … Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical ... to project planning and scheduling. * Cross-Functional Collaboration: Collaborate with verification, physical design , test generation, and milli code teams to… more
    IBM (06/27/25)
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  • Senior RTL Design Engineer

    Capgemini (Austin, TX)
    …+ Debugging behavioral RTL issues in Mixed-Signal IP + Partnering with the Physical Design team to resolve timing closure challenges **Required Skills:** We're ... details + Proven experience in PCIe and Ethernet IP integration + Proficiency in AMBA-based bus protocols (CHI, AXI,...SPI, SW, JTAG, and I2C + Solid fundamentals in VLSI design + Sharp problem-solving and data… more
    Capgemini (07/12/25)
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  • Analog Design & Layout Engineer

    University of Southern California (Los Angeles, CA)
    …and sensing applications such as 5G/6G and related domains to advanced digital design . The Prototype Integration and Engineering Services (PIES) team will ... in one or more of the following: analog circuit/RF design , digital circuit design , and physical...years Minimum Skills: Thorough knowledge of device physics and VLSI electrical engineering principles at the device and circuit… more
    University of Southern California (07/16/25)
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  • SMTS, Memory Design Engineer

    Micron Technology, Inc. (Richardson, TX)
    …support the efforts of groups such as Product Engineering, Test, Probe, Process Integration , Assembly and Marketing to proactively design products to optimize ... experience in Computer or Electrical Engineering + CMOS Circuit Design , VLSI , and Analog Circuit Design...+ Knowledge and experience using Cadence Virtuoso + Understanding Physical Layout & Circuit Floor Planning + Experience simulating… more
    Micron Technology, Inc. (06/12/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. + Take part in floor planning, custom ... from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior...mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed… more
    NVIDIA (07/24/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. + Take part in floor planning, custom ... you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a...mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed… more
    NVIDIA (07/17/25)
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  • SoC Power/Performance Post-Si Validation…

    Qualcomm (San Diego, CA)
    …supervision. **Preferred Qualifications:** + Strong familiarity with Static Timing Analysis and Physical Design tools & methodology. + Solid understanding of ... + Solid foundational knowledge in Electronics and Electrical Engineering principles, VLSI concepts, digital/ASIC design , and packaging including chiplets +… more
    Qualcomm (06/04/25)
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