• ASIC Implementation Engineer - Timing

    Meta (Austin, TX)


    Summary:

    Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.

    Required Skills:

    ASIC Implementation Engineer - Timing Responsibilities:

    1. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC.

    2. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.

    3. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes.

    4. Perform STA for full chip and Physical partition blocks using PrimeTime

    5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.

    6. Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA).

    7. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks.

    8. Interact with Physical Design Engineers and provide them with timing feedback.

    Minimum Qualifications:

    Minimum Qualifications:

    9. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

    10. 5+ years of experience with STA tools

    11. Experience with developing full chip flat & hierarchical timing constraints

    12. Experience with AOCV/POCV timing analysis , SI noise analysis

    13. Experience with running Static Timing Analysis for full chip using DMSA

    14. Knowledge of front-end and back-end ASIC flows

    15. Experience with communicating across functional internal teams and vendors.

    Preferred Qualifications:

    Preferred Qualifications:

    16. Experience with SOC Design Integration & Front End Implementation

    17. Experience with Front End Synthesis tools such as Design Compiler, Genus

    18. Experience with Back End PD tools such as Fusion Compiler, Innovus

    19. Experience with Understanding RTL design using SystemVerilog or other HDL.

    20. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows

    21. Knowledge of Timing/physical libraries, SRAM Memories.

    Public Compensation:

    $142,000/year to $203,000/year + bonus + equity + benefits

    **Industry:** Internet

    Equal Opportunity:

    Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

     

    Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].