• ASIC Engineer, EDA Infrastructure

    Meta (Sunnyvale, CA)


    Summary:

    Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure organization. We are looking for individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications.

    Required Skills:

    ASIC Engineer, EDA Infrastructure Responsibilities:

    1. Front End implementation flow development and support

    2. Physical Design implementation flow development and support

    3. RTL2GDS flow development and support

    4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation

    5. Work with EDA vendors on new tools/technology and new features evaluation and adoption

    6. Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance

    7. Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance

    8. Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting

    Minimum Qualifications:

    Minimum Qualifications:

    9. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

    10. 8+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments

    11. Knowledge of front-end and back-end ASIC tools and flows

    12. Experience with communicating across functional internal teams and with vendors

    Preferred Qualifications:

    Preferred Qualifications:

    13. Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support

    14. Experience with RTL design using SystemVerilog or other HDL

    15. Experience setting up EDA infrastructure from scratch

    16. Experience with developing and supporting solutions for ASIC design environment and infrastructure

    Public Compensation:

    $173,000/year to $249,000/year + bonus + equity + benefits

    **Industry:** Internet

    Equal Opportunity:

    Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

     

    Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].