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Job Title: Physical Verification Engineer (ASIC Design)

Role Overview

As a **Physical Verification Engineer** , you will be responsible for ensuring that ASIC layouts meet all foundry design rules and manufacturing requirements. You will own the sign-off verification process — performing DRC, LVS, ERC, and other checks to ensure design integrity, manufacturability, and compliance with foundry specifications. Working closely with layout, physical design, and CAD teams, you’ll help deliver clean, tape-out–ready GDS data for complex SoC and ASIC designs.

Key Responsibilities

+ Perform **physical verification** of full-chip and block-level layouts, including:

+ **DRC (Design Rule Check)**

+ **LVS (Layout vs. Schematic)**

+ **ERC (Electrical Rule Check)**

+ **Antenna checks** , **Density checks** , and **metal fill verification**

+ Debug and resolve DRC/LVS violations by collaborating with physical design, layout, and circuit design teams.

+ Execute **foundry sign-off** checks using advanced process technology nodes (e.g., 5nm, 7nm, 16nm).

+ Manage and maintain **PV runsets** , verification scripts, and rule decks provided by foundries.

+ Automate repetitive tasks and improve verification efficiency using **Tcl, Python, or Perl** scripting.

+ Validate **hierarchical verification flows** (chip-level and block-level integration).

+ Ensure compliance with **electromigration (EM)** , **IR drop** , and **reliability** requirements in conjunction with sign-off teams.

+ Support **tape-out preparation** , including GDS merging, data integrity checks, and final report generation.

+ Collaborate with CAD and methodology teams to refine verification flows and integrate new EDA tools or rule decks. **Qualifications** **Education:**

+ Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. **Experience:**

+ 10+ years of experience in ASIC or SoC **physical verification** or **layout sign-off** .

+ Hands-on experience with **sign-off tools** such as:

+ **Mentor Graphics Calibre** (Calibre DRC/LVS/PERC)

+ **Synopsys ICV / Hercules**

+ **Cadence Pegasus / Assura**

+ Familiarity with **advanced CMOS technology nodes** and foundry rule decks.

+ Understanding of **physical design flows** (floorplanning, place & route, extraction, and timing closure). **Technical Skills:**

+ Strong proficiency in **Tcl, Python, or Shell scripting** for automation.

+ Experience with **GDSII/OASIS** data formats and layout editing tools (e.g., Virtuoso, KLayout, or ICC2 GUI).

+ Knowledge of **PDK (Process Design Kit)** components and foundry deliverables.

+ Understanding of **timing** , **power** , and **signal integrity** interactions from a physical verification standpoint. **Soft Skills**

+ Strong analytical and problem-solving abilities for root-cause debugging of complex layout issues.

+ Ability to work collaboratively with cross-functional design and CAD teams under tight tape-out schedules.

+ Detail-oriented with a commitment to producing sign-off–quality results.

+ Clear communication and strong documentation skills. **Preferred Experience (Nice to Have)**

+ Experience with **multi-voltage designs** and **low-power verification** (UPF/CPF).

+ Familiarity with **DFM (Design for Manufacturability)** and **lithography-aware verification** .

+ Exposure to **analog/mixed-signal** layout verification.

+ Participation in **full-chip tape-outs** for production silicon.

ManpowerGroup is committed to providing equal employment opportunities in a professional, high quality work environment. It is the policy of ManpowerGroup and all of its subsidiaries to recruit, train, promote, transfer, pay and take all employment actions without regard to an employee's race, color, national origin, ancestry, sex, sexual orientation, gender identity, genetic information, religion, age, disability, protected veteran status, or any other basis protected by applicable law.