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Overview

Defines and drives project goals across the product lifecycle. Generates or contributes to single/multiple project implementation schedules and anticipates project implementation issues. Ensures understanding of quality that ensure best-in-class final outputs/products/designs. Recommends processes, document needs, and policies related to training programs and drives the creation of documents and templates across teams. Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels. Improves verification efficiency through new and updated methodologies or tools. Defines roadmaps for all intellectual property (IP) components, including high-level and detailed architecture features, through collaboration with internal customers and teams. Assesses and refines the architecture to optimize for product goals, with consideration for area, power, and performance. Authors architectural specification to represent the vision of the product for key consuming partner architects, IP providers, as well as firmware (FW), design, and verification engineers. Partners with Micro-architects and RTL teams to define vectors/benchmarks to track and characterize performance for different use cases. Defines the micro-architectural implementation specification for a functional block.

Responsibilities

Architecture

Assesses and refines the architecture to optimize for product goals, with consideration for area, power, and performance. Provides technical leadership and influences system on chip (SoC) design or IP algorithm and architecture to achieve performance and efficiency goals. Understands product requirements. Designs architecture that adheres to product requirements with consideration for Power, Performance, and Area (PPA). Executes analyses and modeling to ensure the architecture proposal aligns with PPA objectives. Creates initial architecture specifications. Provides initial versions of architectural models for use by architects to validate the architecture, and by design/DV teams to validate implementation.

Partners with Micro-architects and RTL teams to define vectors/benchmarks to track and characterize performance for different use cases. Leverages security threat models to architect secured access paths.

Authors architectural specification to represent the vision of the product for key consuming partner architects, IP providers, as well as firmware (FW), design, and verification engineers.

Defines roadmaps for all intellectual property (IP) components, including high-level and detailed architecture features, through collaboration with internal customers and teams (e.g., product-architecture and product-management teams).

Circuit Design

Drives design and collateral delivery of low power analog mixed signal, memory, or custom digital circuits such as Receiver front-end, regulators, and Digital-to-Analog Converters (DACs), SRAM, register files, and standard cells in cutting edge technology. In collaboration with system architect, develops innovative digital and analog mixed signal circuit solutions and collateral delivery to meet design criteria (e.g., power, area, frequency, bandwidth, noise, linearity, jitter, mismatch). Designs circuits with signal, power integrity, and yield considerations in mind and makes necessary design tradeoffs. Leads layout optimization on advanced process technologies for volume production, checking for quality, electromigration and IR (Voltage) drop (EMIR), design for manufacturing (DFM), and yield.

Computer Assisted Design (CAD)

Develops and implements technical solutions to complex quality and design challenges and applies lessons learned to recommend future-focused solutions.

Applies deep knowledge in a specific and complex engineering domain, or knowledge in multiple technical areas. Shares and acquires advanced knowledge of industry trends, competitor products, the customer experience, and advances in various engineering fields. Shows global tradeoffs across trends and where Microsoft wants to direct the electronic design automation (EDA)/silicon industry. Deploys technologies with longer term strategy for further development.

Provides make-vs.-buy recommendations based on complexity, financial impact, quality, reliability, and time duration, influencing decision makers and stakeholders.

Refines the architecture or the sub-component of the architecture of the silicon CAD flow.

Creates designs and/or verification plans that are robust, scalable, extensible, and complex. Develops technology and product roadmaps. Takes a lead role in execution of complex designs.

Creates intellectual property and technical due diligence.

Uses performance instrumentation and presents results and insights to team and architects. Makes and implements recommendations for software optimization to architects and management. Drives systematic methodology changes across teams to improve turn-around-time of the flow.

Researches new tools, technologies, or methods. Determines which tools & capabilities are required to successfully deliver on project requirements and distributes those tools across product units. Converges non-standard implementations to one. Collaborates and strategizes with tool vendors to coordinate releases, testing, and capabilities necessary to execute multiple projects.

Design

Identifies potential intellectual property, conducts technical due diligence, and encourages other engineers to file patent designs. Encourages wider adoption of intellectual property and/or licensing throughout the industry. May file patents and complete necessary patent document.

Provides recommendations for difficult or complex make-versus-buy decisions based on complexity, financial impact, quality, reliability, and time duration. Influences decision making with wider decision makers and stakeholders.

Logic Design

Conducts, reports, and mentors team on design quality results from quality checks (e.g., functional quality through design exercise, Lint, Clock Domain Crossing [CDC], Reset Domain Crossing [RDC], RTLA, and low-power intent).

Mentors the team to support work with chip architects to understand architectural goals and integrate new methodologies or tools across team. Works with performance modeling teams to develop innovative ideas for IP.

Defines the micro-architectural implementation specification for a functional block. Holds responsibility for the documentation and education of other teams (e.g., DV, Firmware). Leads the complex design and integration of sub-system intellectual property (IP) and functional blocks into system on chip (SoC) design via industry standard tools. Drives the integration and microarchitecture of SoC designs, including the development and refinement of digital interfaces and subsystems.

Manufacturing and Testing

Leads, Architects and drives development of the hardware and software infrastructure/implementation for Automated Test Equipment (ATE), system level test (SLT), and system to tester correlation activities. Leads test features & content definition and acts as domain expert. Co-engineers with outsourced semiconductor assembly and test (OSAT) in areas of Manufacturing Test Pathfinding and running proof-of-concept through test vehicles. Leads definition and execution of quality, reliability, and foundry technology. Develops innovative methodologies for pre-silicon technology and product requirements. Defines test chip roadmap. Leads vendor selection and product qual strategy definition, defect reduction strategy, cross functional influence across design, design for test (DFT), technology for reliability, availability, and serviceability (RAS) improvement and defective parts per million (DPPM) mitigation. Connects system on chip (SoC) reliability (silicon/package/high bandwidth memories (HBM)) to system level reliability requirements. Leads end-to-end engineering samples delivery from silicon to platform with on-time schedule, required quantities, and required product quality and feature, with direct customer and OSAT engagements. Leads resolution and mitigation of any excursion events in manufacturing flow and drives roadmap execution of manufacturing health indicators (MHI) such as yield and test time. Connects engineering strategy to business value.

Leads architecture, development and deployment of artificial intelligence (AI)/machine learning (ML) based smart manufacturing flow. Ensures ATE platform meets PnP and cost optimization. Leads test content and module development and bring up on tester across PVT which covers coverage, debug, quality, and characterization. Leads cross-functional teams to solve problems and collaborate with internal and external teams. Leads product qualification, reliability and maintainability analysis (RMA), and sustaining activities. Develops key performance indicators (KPIs) to monitor and identify issues. Proactively identifies gaps and develops capabilities to close those gaps. Utilizes datacenter telemetry as a differentiator for silicon. Works across the organization to monitor and improve datacenter reliability to achieve best in class reliability and customer excellence. Leads end-to-end engineering samples delivery from silicon to platform with on-time schedule, required quantities and required product quality and feature, with direct customer and OSAT engagements. Leads resolution and mitigation of any excursion events in manufacturing flow and drives roadmap execution of manufacturing health indicators (MHI) such as yield and test time.

Packaging

Directs layout tools (e.g., Computer-Aided Design [CAD]) and drives the development/completion of substrate/interposer designs for packaging of high-performance silicon designs, in collaboration with cross-site, multi-disciplinary teams. Develops packaging solutions and electrical models supporting overall system performance requirements, in collaboration with partner teams (e.g., silicon, intellectual property [IP], socket, thermal and system design). Completes substrate/Interposer design verification and documentation for successful tape-out at external factories.

Drives definition of package configurations, including signal pinouts and IO floorplans, to meet system and form-factor requirements. Executes the co-design and co-optimization of silicon package platforms and systems. Drives technology capability assessment across the industry and recommends product alignment. Drives the supplier selection process. Develops design guidelines for substrate/interposer and packaging technology platforms.

Executes technology development with industry partners using test vehicles to enable product readiness and drives for quality output. Directs updates and changes to models or designs, and executes technology/ product qualification according to established methodology (e.g. HTS, TCx, HAST, etc.).

Performance

Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs. Determines type of performance model needed and appropriate model fidelity. Leads development of the performance model. Organizes analysis of workload information to identify performance bottlenecks. Collaborates across functions to propose architectural/microarchitectural changes and provide quantitative justification. Leads verification of correlation of system on chip (SoC) performance models to RTL implementation.

Physical Design

Leads partition floor planning to achieve optimal Power, Performance, and Area results. Drives team execution of physical design-architecture solutions, across product lines or multiple product groups, that account for design trends and future concepts. Leads execution from synthesis to place and route of partitions through all signoff stages (e.g., timing signoff, physical verification, electromigration and IR (Voltage) drop (EMIR) signoff, Formal Equivalence, and Low Power Verification). Drives the development of future power delivery solutions for chiplet architecture with advanced packaging and advanced silicon nodes. Develops robust clock distribution solutions using appropriate methods that meet design requirements.

Delivers analog design intellectual property (IP) to support power delivery solutions.

Post-Silicon Validation

Drives development of tools/scripts and guides team to implement silicon debug tools and capabilities, such as crash dumps, register dumps, triggers and tracing, and closed chassis/remote debug.

Develops comprehensive, full-chip validation strategy, requirements, environments, tools, and methodologies, including debug board, hardware/software, and lab requirements. Organizes creation of content to run on both bare metal and operating system (OS) environments (e.g., synthetic system on chip (SoC) validation targeting Core, Coherency, Memory, Input/Output (I/O), Accelerators, Security).

Pre-Silicon Verification

Improves verification efficiency through new and updated methodologies or tools. Defines verification strategies and test plans.

Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels. Drives the development of verification environments, runs, and debugs simulations to drive quality. Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff. Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals.

Silicon Engineering

Recommends processes, document needs, and policies related to training programs and drives the creation of documents and templates across teams. Identifies where training is beneficial and coordinates training. Reviews work and documentation developed by less experienced engineers. Reads and writes device and/or product specification sheets that meet internal and external documentation needs. Suggests modifications for internal and external device and/or product specifications and data sheets based on expertise. Identifies ways to add value to existing products and testing procedures.

Defines and drives project goals across the product lifecycle. Develops the project methodology by defining the tools, flows, and methods to be used. Develops and leverages expertise with complex features/flows/protocols to identify critical paths and address them in product plans across all milestones for current project. Leads engagement with partners to drive or implement improvements to prevent, reduce, and/or find issues. Identifies and plans for involvement of cross-functional teams and external vendors, ensuring alignment and end-to-end optimization of silicon, system designs, and software.

Ensures understanding of quality that ensure best-in-class final outputs/products/designs. Leads the development of strategies, end-to-end methodologies, test plans, and tools that will ensure quality standards and expectations are being met. Implements plans and methodologies for tracking and ensuring quality, as well as identifying and addressing issues, across project work. Leads the identification and incorporation of insights and lessons learned to improve quality and minimize issues in current and future projects. Drives collaboration and alignment with partner teams to implement testing plans and methodologies consistently and holistically across groups.

Generates or contributes to single/multiple project implementation schedules and anticipates project implementation issues. Proposes changes to project schedules and designs to mitigate risks. Leads feedback and drives changes to the existing engineering processes within their team, participating in discussion outside their team. Reviews third party, complex intellectual property data sheets against requirements. Evaluates external supplier or partner quality and resources, monitoring execution to plan, in order to ensure successful delivery. Reviews key details of external supplier or partner products to support product development. Makes external supplier or partner selection decisions. Drives efforts to identify and resolve complex problems with internal and external teams during project execution. Drives implementation of new initiatives with external vendors. Drives teams on the anticipation and mitigation of significant project risks and issues (e.g., external supplier or partner delays, spec gaps, or methodology/tool issues) throughout the project. Incorporates learnings from previous projects and brings in expertise when needed to resolve issues. Monitors project progress/status across one or more project teams, anticipates potential challenges, and shares project progress details with key stakeholders as necessary.

Qualifications

Required/Minimum Qualifications

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

+ OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

+ OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

+ OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

+ 3+ years of SOC or IP design related experience across advanced technology nodes

+ 5+ years of SOC or IP Program Management experience

+ 12+ years of technical engineering experience

+ Experience negotiating and working with industry Silicon IP vendors through the entire life cycle from definition to post-silicon

+ Experience drafting technical SOWs with 3rd party vendors

+ Demonstrated hands-on technical leadership such as creating bottom’s up schedules, coordinating work across a team, driving IP milestone closure, or solving cross-team technical problems

+ Experience with IP quality assurance and IP milestone acceptance criteria

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. (https://careers.microsoft.com/v2/global/en/accessibility.html)