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Physical Design Engineer, 3D Technology, PhD, University Graduate

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

+ PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

+ Academic, educational, internship, or project experience with physical design and 3D integration technologies such as 3D-IC, 2.5D, chip stacking, vertical stacking, integrity, or Through-Silicon Vias (TSV).

+ Experience with running industry standard tools for chip design (e.g., from Synopsys, Cadence, or Siemens EDA).

Preferred qualifications:

+ Experience with advanced finfet and gate-all-around technology nodes, and enabling physical design flows in these nodes.

+ Experience in delivering optimized digital place-and-route blocks leading to test chip or product tapeouts.

+ Experience with programming/scripting (TCL, Python, or Perl).

+ Expertise with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces.

+ Understanding of standard cells, SRAMs, power, noise, and IR analysis.

+ Excellent presentation and communication skills.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Engineer in 3D Technology, you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore’s Law while delivering ASIC’s and SoC’s. You will help develop new 3D technology physical design methodologies to drive best product Power Performance Area (PPA) by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs. You will drive new physical design flows that co-optimize across the entire design methodology space, including 3D and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with through-silicon vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more aboutbenefits at Google (https://careers.google.com/benefits/) .

Responsibilities

+ Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.

+ Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.

+ Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.

+ Work with our physical design, technology, circuits, and architecture teams and IP partners in advanced Complementary Metal-Oxide-Semiconductor (CMOS) nodes.

+ Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See alsoGoogle's EEO Policy (https://www.google.com/about/careers/applications/eeo/) ,Know your rights: workplace discrimination is illegal (https://careers.google.com/jobs/dist/legal/EEOC\_KnowYourRights\_10\_20.pdf) ,Belonging at Google (https://about.google/belonging/) , andHow we hire (https://careers.google.com/how-we-hire/) .

If you have a need that requires accommodation, please let us know by completing ourAccommodations for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.