- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , SoC Verification Responsibilities: 1. Define and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Performance & Package Verification Responsibilities:… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Palo Alto Networks (Santa Clara, CA)
- …and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ... You will work on diverse platforms including simulation, emulation, formal verification , and silicon validation. We expect...- MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in… more
- Google (Sunnyvale, CA)
- ASIC Design Verification Engineer ,...or formally verify designs with SVA and industry leading formal tools. + Identify and write all types of ... focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will use design and verification … more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year… more
- Amazon (Hawthorne, CA)
- …preferably in areas of image processing. - Familiarity with Matlab - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more