- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... what's possible! Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding...with Spyglass CDC and glitch analysis * Experience using Formal Verification : Synopsys Formality and Cadence LEC.… more
- Meta (Sunnyvale, CA)
- …Estimation at RTL and Gate Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and debug the ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Meta (Sunnyvale, CA)
- …Estimation at RTL and Gate Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and debug the ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Broadcom (San Jose, CA)
- …* Synthesis using Synopsys tool suite * Timing Analysis using Synopsys Primetime tool * Formal Verification * DFT concepts of Scan, BIST. * Strong Perl and Tcl ... challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems. 10. Experience with Synthesis, Timing Closure and Formal Verification Methodology. 11. Master's or PhD… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 12. Experience with Synthesis, Timing Closure and Formal Verification Methodology 13. Master's or PhD… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... at RTL & gate level and identify power reduction opportunities. 4. Run formal verification checks between RTL & gate level netlist and debug aborts, inconclusive… more
- Cisco (San Jose, CA)
- …Cadence) * Experience with Spyglass CDC and glitch analysis * Experience using Formal Verification : Synopsys Formality and Cadence LEC. * Experience with ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Amazon (San Diego, CA)
- …Familiarity with UVM and Matlab . Ability to write assertions and exposure to Formal verification Amazon is an equal opportunity employer and does not ... blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification including test plan development . Assist with debug and… more