• Principal Design Engineer Manager - AI…

    Microsoft Corporation (Mountain View, CA)
    …/ Machine Learning (ML) SoCs + Working knowledge of writing assertions, coverage and formal verification Silicon Engineering M5 - The typical base pay range for ... and optimize the Cloud infrastructure. We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team. Microsoft's mission is… more
    Microsoft Corporation (09/26/25)
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  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …flow, preferably on Genus and Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure for ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong… more
    Cadence Design Systems, Inc. (09/09/25)
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  • Physical Design Methodology Engineer…

    Amazon (Cupertino, CA)
    …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our… more
    Amazon (09/02/25)
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  • SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of ... * Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip / Sub-System STA and… more
    Amazon (08/01/25)
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