- Meta (San Diego, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation. 11.… more
- Siemens (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... across a range of areas from application engineering support and management, verification and validation of complex semiconductor ICs, system testing, and beyond? If… more
- Qualcomm (Santa Clara, CA)
- …timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification . The individual also should have deep knowledge on ... Compiler - Timing closure experience in Synopsys PTSI - Formal verification experience - Power domain analysis...Science, Engineering, or related field and 6+ years of ASIC design, verification , validation, integration, or related… more
- Amazon (Cupertino, CA)
- …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and… more
- Google (Sunnyvale, CA)
- …and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification , Change Data Capture (CDC), and power analysis. + ... high speed clock distribution circuits. + Experience in Spice simulations, clock verification , and signoff. Preferred qualifications: + Experience in ASIC … more
- NVIDIA (Santa Clara, CA)
- …based SOCs + Prior hands-on experience in Ada/SPARK programming (including specification and formal verification ) and TLA+ formal verification modeling ... an exciting opportunity for a talented Senior System Software Engineer to join our dynamic Automotive Team and help...strong C and/or Ada/SPARK programming skills, and experience with formal methods, we want to hear from you! Join… more
- Qualcomm (San Diego, CA)
- …Group, Engineering Group > Video Systems, HW Architecture **General Summary:** As a Verification Engineer , you will be responsible for understanding the expected ... architects of these multimedia systems, as well as multimedia ASIC designers and SW engineers to plan and execute...synthesizable models for emulation in Verilog/SV + Experience in formal verification is plus + Experience in… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... physical design, and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level of expertise in PD… more
- NVIDIA (Santa Clara, CA)
- …CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools + Have a strong background in Perl and ... hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades....you'll be doing: + You will be working with ASIC controller teams to define a unified interface +… more
- Amazon (Cupertino, CA)
- …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our… more