• Low Power Design/Methodology Engineer

    Qualcomm (San Diego, CA)
    …analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. + Work closely with technology/circuit ... in Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related work experience. OR Master's degree in… more
    Qualcomm (05/15/25)
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  • Power Management Design Engineer

    Qualcomm (San Diego, CA)
    …designs + Experience in Spyglass Lint/CDC checks and waiver creation + Experience in formal verification with Cadence LEC + Understanding of full RTL to GDS ... Synthesis & PD teams for design convergence. **Skills/Experience Sr Engineer / Staff Engineer ** + 5 to...Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related… more
    Qualcomm (07/16/25)
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  • RTL Design Engineer

    Qualcomm (San Diego, CA)
    …Verilog or System Verilog coding + Familiarity with front-end design flows (synthesis, formal verification , static timing analysis, CDC) is a plus **Minimum ... (CDC) check + Synthesis and Static Timing Analysis + Formal and functional verification + Lint check...Science, Engineering, or related field and 6+ years of ASIC design, verification , validation, integration, or related… more
    Qualcomm (06/24/25)
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  • I/O Modeling and Characterization Engineer

    Qualcomm (San Diego, CA)
    …of advanced verification methodologies, including SystemVerilog Assertions (SVA), power-aware verification , and formal verification techniques. + Own and ... in Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related work experience. OR Master's degree in… more
    Qualcomm (06/27/25)
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  • Custom IP Design Engineer

    Qualcomm (San Diego, CA)
    …plus. + Variation-aware design experience is a plus. + Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus. **Minimum Qualifications:** ... in Science, Engineering, or related field and 2+ years of ASIC design, verification , validation, integration, or related work experience. OR Master's degree in… more
    Qualcomm (06/27/25)
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  • Sr. Physical Design Engineer , Annapurna…

    Amazon (Cupertino, CA)
    …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and… more
    Amazon (06/04/25)
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  • SOC Physical Design Engineer , Hardware…

    Amazon (Sunnyvale, CA)
    …block and Sub System level. - Drive block physical implementation through synthesis, formal verification , floor planning, bus / pin planning, place and route, ... Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our...Graphics, Synopsys, or Others) to block design for synthesis, formal verification , floor planning, bus / pin… more
    Amazon (07/03/25)
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  • SDC Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC ...in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical… more
    Arrow Electronics (06/06/25)
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  • Principal Design Engineer Manager - AI…

    Microsoft Corporation (Mountain View, CA)
    …/ Machine Learning (ML) SoCs + Working knowledge of writing assertions, coverage and formal verification Silicon Engineering M5 - The typical base pay range for ... and optimize the Cloud infrastructure. We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team. Microsoft's mission is… more
    Microsoft Corporation (07/18/25)
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  • Senior Digital Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools + Have a strong background in Perl and ... hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades....you'll be doing: + You will be working with ASIC controller teams to define a unified interface +… more
    NVIDIA (06/08/25)
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