- Cadence Design Systems, Inc. (San Jose, CA)
- …flow, preferably on Genus and Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure for ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong… more
- Qualcomm (San Diego, CA)
- …will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification , PLDRC, clock domain crossing, and low power ... and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the...low power team on power optimization + Work with verification team to collaborate on test plan, coverage plan,… more
- Qualcomm (San Diego, CA)
- …detailed issues + Be Familiar with The latest EDA tools for synthesis, formal verification , timing analysis and physical design **Minimum Qualifications:** * ... Engineering Group > GPU ASICS Engineering **General Summary:** The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible… more
- Amazon (Cupertino, CA)
- …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our… more
- NVIDIA (Santa Clara, CA)
- …We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... environments that are scalable, reusable, and validated through both structural and formal processes for constraint correctness + Analyze RTL clock constructs to… more
- Amazon (Sunnyvale, CA)
- …powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of ... * Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip / Sub-System STA and… more