• ASIC /FPGA Design Engineer…

    Teradyne (North Reading, MA)
    …better business results. Opportunity Overview Our Hardware Engineering team is seeking an FPGA/ ASIC Design Engineer to work with a multi-disciplined team ... environment. + Deriving requirements from higher level specifications + Writing design documents + Designing and implementing register-transfer-level ( RTL ) code… more
    Teradyne (08/26/25)
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  • Sr. ASIC Design Engineer…

    Amazon (North Reading, MA)
    …performance, and area for significant IPs early in design cycle -Execute on design specifications to deliver high quality RTL -Ensure quality by running and ... tracking results of front-end tools including: Synthesis, Lint ( RTL , DFT, UPF), Power Analysis and STA -Take the...to volume production -Hands on experience in low power design techniques -Strong written and verbal skills Preferred Qualifications… more
    Amazon (07/10/25)
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  • Senior ASIC Verification Engineer…

    NVIDIA (Westford, MA)
    …the next era of AI computing. What You'll Be Doing: + Drive the verification of ASIC design and architecture for NVLink HSIO controllers at the IP and sub-system ... NVIDIA is seeking a highly motivated Senior Design Verification Engineer to play a...test plans, and building the infrastructure required to ensure design correctness. + Work closely with architects, RTL… more
    NVIDIA (09/12/25)
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  • Senior ASIC Timing Engineer

    Cisco (Maynard, MA)
    Senior ASIC Timing Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1449290) + Location:Maynard, Massachusetts, US + Area of InterestEngineer - ... are received. **Meet the Team** Join our team at Acacia, where we design advanced optical transceivers for high-speed fiber optic transmission in data centers and… more
    Cisco (08/21/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and...+ Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing… more
    NVIDIA (08/13/25)
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  • Hardware FPGA Design Engineer

    Cisco (Maynard, MA)
    …synthesis tools for FPGAs** + **Expertise in creating FPGA implementations from ASIC RTL code** + **Expertise in digital design of standard cell ASICs** + ... Hardware FPGA Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444830) + Location:Maynard,... ASIC Blocks** + **Contribute to our custom ASIC RTL code** **Minimum Qualifications:** + **Bachelors… more
    Cisco (09/24/25)
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