• RF Module Engineer - Summer/Fall Co-Op

    Skyworks (San Jose, CA)
    …from initial concept to final production, whether your specialty is in multi- chip modules, power amplifiers, RFICs or PMICs, RF filters, Validation, Test, Product ... and highly competitive cellular handset market. + As a Multi- Chip Module Design Engineer, you will be responsible for...Skills + Available to start June/July 2026 working 40 hours per week in 6 month co-op role +… more
    Skyworks (08/16/25)
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  • Staff Semiconductor Process Engineer

    Lockheed Martin (Goleta, CA)
    …wicking, plasma system, substrate thinning, dicing, Anti\-Reflection \(AR\) coating, and flip\- chip bonding for hybridization, a key step in the manufacturing ... in a cleanroom environment with demonstrated expertise in either flip\- chip hybridization techniques or related processes, such as epoxy...flexibility to our employees\. Schedules range from standard 40 hours over a five day work week while others… more
    Lockheed Martin (08/21/25)
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  • Sr. IC Layout Designer (Silicon Engineering)

    SpaceX (Irvine, CA)
    …at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: + Work with the ... integrated circuit designers and chip leads to determine the chip floor...ADDITIONAL REQUIREMENTS: + Must be willing to work extended hours and weekends as needed to meet critical milestones… more
    SpaceX (09/02/25)
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  • Poker Chiprunner - Poker

    Sycuan (El Cajon, CA)
    …+ High School Diploma, High School Certificate of Completion, or GED + Chip runner experience + Poker player experience + Office receptionist experience Skills and ... Knowledge: Essential: + Basic understanding of chip use and chip denominations applicable to...Ability to walk and stand for up to six hours at a time + Ability to lift up… more
    Sycuan (08/08/25)
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  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    …design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for ... of ASIC or related experience. + Experience with block/full chip SDC development in functional and test modes. +...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (08/14/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key ... multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (07/22/25)
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  • Wireless Modem Verification Engineer (Silicon…

    SpaceX (Irvine, CA)
    …by using Python and MATLAB programs + Contribute towards pre-silicon verification, chip bring-up and post-silicon validation + Be a hands-on self-starter who can ... + Experience with scripting languages, eg Python for automation + RTL design, chip bring-up, and post-silicon validation experience + Ability to work in a dynamic… more
    SpaceX (09/02/25)
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  • Payroll Administrator CVDC

    Adecco US, Inc. (Shafter, CA)
    …annual/bi-annual Focal Review increases are entered accurately into Kronos. Ensures the Blue Chip data is provided to agency and Corporate Payroll as required. + ... Exception reports to clear missed punches in Kronos, missing hours to finance by 9:00am daily + Weekly/Monthly reports:...Kronos dept. listing. + Compile and submit Exempt Blue Chip and Supervisor Saturday Worked bonus files. + Provide… more
    Adecco US, Inc. (08/21/25)
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  • Road Maintenance Supervisor III

    Mendocino County Sheriff's Office (Fort Bragg, CA)
    …be completed within two years. Participation is required and completed during work hours . Job Requirements and Minimum Qualifications Duties may include but are not ... to projects and programs such as: dust suppression, vegetation management, chip seals, asphalt overlays, striping and grading, stormwater, and corrective… more
    Mendocino County Sheriff's Office (08/23/25)
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  • Senior Analog/mixed-signal IC Design Engineer…

    Cisco (San Jose, CA)
    …CMOS products. + You will lead efforts for a large block on a complex chip , mentor team members and track deliverables, participate in peer review of complex IC ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
    Cisco (08/23/25)
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