• RF Module Engineer - Summer/Fall Co-Op

    Skyworks (San Jose, CA)
    …from initial concept to final production, whether your specialty is in multi- chip modules, power amplifiers, RFICs or PMICs, RF filters, Validation, Test, Product ... and highly competitive cellular handset market. + As a Multi- Chip Module Design Engineer, you will be responsible for...Skills + Available to start June/July 2026 working 40 hours per week in 6 month co-op role +… more
    Skyworks (08/16/25)
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  • ASIC Design Engineer - Design & Timing Constraints

    Cisco (San Jose, CA)
    …heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create ... will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (08/15/25)
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  • Poker Chiprunner - Poker

    Sycuan (El Cajon, CA)
    …+ High School Diploma, High School Certificate of Completion, or GED + Chip runner experience + Poker player experience + Office receptionist experience Skills and ... Knowledge: Essential: + Basic understanding of chip use and chip denominations applicable to...Ability to walk and stand for up to six hours at a time + Ability to lift up… more
    Sycuan (08/08/25)
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  • Sr. RFIC Layout Designer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: + Work with the ... integrated circuit designers and chip leads to determine the chip floor...ADDITIONAL REQUIREMENTS: + Must be willing to work extended hours and weekends as needed to meet critical milestones… more
    SpaceX (06/19/25)
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  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    …design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for ... of ASIC or related experience. + Experience with block/full chip SDC development in functional and test modes. +...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (08/14/25)
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  • ASIC Verification Engineer

    Cisco (San Jose, CA)
    …with front-end RTL Design and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and ... of simulation models, test plan, code or functional coverage, multi- chip /system simulation, and performance analysis. Minimum Qualifications: + BSEE/CS...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (07/25/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key ... multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (07/22/25)
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  • Hardware Modeling Engineer

    Cisco (San Jose, CA)
    …Your work will enable the infrastructure to support the entire chip design process, enhancing simulation accuracy, performance, and multi-functional collaboration. + ... verification teams from initial definition to signoff of the chip + Work closely with software teams to bring...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (07/09/25)
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  • Technical Leader ASIC Design - Prototyping

    Cisco (San Jose, CA)
    …heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create ... closely with Design, DV, and Software teams to understand chip architecture and effectively prototype the SoC on the...time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in… more
    Cisco (06/25/25)
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  • Scientist, Functional Sciences

    Bristol Myers Squibb (Redwood City, CA)
    …co-cultures, organoids, human derived iPSC, primary cells, micropatterned 2D culture, tissue-on-a- chip , or other 3D models. + Design scalable assays with ... co-cultures, primary cells, human derived iPSC, organoids, 3D or tissue-on-a- chip , is required. + Hands-on experience with HCI or...between Christmas and New Year's holiday, up to 120 hours of paid vacation, up to two (2) paid… more
    Bristol Myers Squibb (08/14/25)
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