- Adecco US, Inc. (Moreno Valley, CA)
- …annual/bi-annual Focal Review increases are entered accurately into Kronos. Ensures the Blue Chip data is provided to agency and Corporate Payroll as required. + ... Exception reports to clear missed punches in Kronos, missing hours to finance by 9:00am daily + Weekly/Monthly reports:...Kronos dept. listing. + Compile and submit Exempt Blue Chip and Supervisor Saturday Worked bonus files. + Provide… more
- SpaceX (Irvine, CA)
- …by using Python and MATLAB programs + Contribute towards pre-silicon verification, chip bring-up and post-silicon validation + Be a hands-on self-starter who can ... + Experience with scripting languages, eg Python for automation + RTL design, chip bring-up, and post-silicon validation experience + Ability to work in a dynamic… more
- Cisco (San Jose, CA)
- …languages (Verilog, SystemVerilog, or VHDL). + Understanding of SoC (System on Chip ) architecture + Experience with lab tools and equipment (oscilloscopes, logic ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Cisco (San Jose, CA)
- …CMOS products. + You will lead efforts for a large block on a complex chip , mentor team members and track deliverables, participate in peer review of complex IC ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Cisco (San Jose, CA)
- …Experience working with cooling or Liquid cooling technologies such as Direct to chip , Immersion cooling. + Experience working with cluster scale testing. Ideally on ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Cisco (San Jose, CA)
- …degree on Electrical Engineering with at least 10 years of experience on ASIC chip design + Prior experience with RTL development on Asynchronous design + Prior ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Cisco (San Jose, CA)
- …software in Python for hardware/ASIC testing. + Prior experience in chip -level, board-level and system-level hardware architecture. + Prior experience in Linux ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Cisco (San Jose, CA)
- …+ Your contribution will be at the center of the entire chip design process, enhancing simulation accuracy, performance, and multi-functional collaboration. + Define ... time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in...Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire… more
- Mendocino County Sheriff's Office (Fort Bragg, CA)
- …be completed within two years. Participation is required and completed during work hours . Job Requirements and Minimum Qualifications Duties may include but are not ... to projects and programs such as: dust suppression, vegetation management, chip seals, asphalt overlays, striping and grading, stormwater, and corrective… more
- Amazon (Cupertino, CA)
- …and many more. The ML Distributed Training team works side by side with chip architects, compiler engineers and runtime engineers to create , build and tune ... value on work-life balance. It isn't about how many hours you spend at home or at work; it's...life-long happiness and fulfillment. We offer flexibility in working hours and encourage you to find your own balance… more