• Senior CAD Engineer, Physical Design

    NVIDIA (Santa Clara, CA)
    …5 years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout , and VLSI design. + Experience working with standard cell ... design & layout . + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a… more
    NVIDIA (07/29/25)
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  • Senior CAD Engineer, Custom Circuit Designers

    NVIDIA (Santa Clara, CA)
    …Engineering and 4+ year's experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design + Excellent programming skills + Experience ... with perl, Cadence SKILL, python, tcl + Great communication skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth,… more
    NVIDIA (06/05/25)
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  • CAD Engineer

    NVIDIA (Santa Clara, CA)
    …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Understanding of version control software ... preferably Perforce. + Understanding the regression testing methodology. + Excellent programming skills; experience with perl, python and other scripting languages. + Great interpersonal skills + Passionate about providing excellent support for end-users.… more
    NVIDIA (06/03/25)
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  • Senior ICV CAD Engineer

    NVIDIA (Santa Clara, CA)
    …5+ years of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL. + Expertise in ICV in order to support, enhance, and debug foundry DRC and LVS techfiles. + Being able to implement NVIDIA specific DFM, DRC rules using ICV. + Add NVIDIA specific devices in the LVS deck using ICV. + Great interpersonal… more
    NVIDIA (06/03/25)
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  • Lead Layout Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …and layout design. + Deep understanding of digital and analog circuit layout concepts in submicron CMOS technologies. + Strong background with Cadence custom ... on all the NVIDIA products! What you'll be doing: + Perform physical layout for custom embedded SRAM structures in state-of-the-art sub-micron CMOS technologies… more
    NVIDIA (08/19/25)
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  • Principal Layout Designer, Pathfinding

    Micron Technology, Inc. (Folsom, CA)
    … project. **How To Qualify:** + 14+ years ofproven experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, ... faster than ever. We are searching for a Principal Layout Designer, Pathfinding for Micron's HBM Team in Folsom,...a must. + Should have hands-on experience in crafting layout of critical blocks such as Temperature sensor, PLL,… more
    Micron Technology, Inc. (07/25/25)
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  • Senior Failure Analysis Engineer (Automotive)

    Power Integrations (San Jose, CA)
    …+ Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Preferences will be given ... to candidates who have a thorough understanding of analog, mixed-signal, or power semiconductor operational characteristics and the ability to apply fault isolation techniques at chip level as well as PCB at power supply system level. Education: + Must have BS… more
    Power Integrations (07/08/25)
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  • Analog Design & Layout Engineer

    University of Southern California (Los Angeles, CA)
    …& Layout EngineerApply (https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Marina-Del-Rey-CA/Analog-Design Layout -Engineer\_REQ20164538/apply) Viterbi ... of the following: analog circuit/RF design, digital circuit design, and physical layout implementation. The successful candidate will work directly with MOSIS 2.0… more
    University of Southern California (07/16/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + You are an authority with ... from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join...to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. + You'll work cross… more
    NVIDIA (07/17/25)
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  • Staff RFIC Design Engineer

    Skyworks (Irvine, CA)
    …Noise Amplifiers and RF switches for wireless applications using SOI, SiGe or CMOS technologies. + Develop circuit architecture, design, layout floor-planning, ... including product definition, architecture, system, transistor-level circuit design, MCM design, layout / layout supervision, lab debug and production support ,… more
    Skyworks (07/09/25)
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