• Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    Physical Design Flow and Methodology Engineer + _link_ Copy link + _email_ Email a friend _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to.... **Responsibilities** + Architect and implement next generation Physical Design EDA CAD tool workflows for ASIC… more
    Google (09/28/25)
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  • Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …solutions and driving tool decisions. - Experience in high-performance, low- power physical design , and implementation techniques with industry standard ... for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation...and drive efforts to resolution. - Work with EDA tool vendors to evaluate new tools, solve bugs, improve… more
    Amazon (09/02/25)
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  • Senior ASIC Floorplan Design

    NVIDIA (Santa Clara, CA)
    …+ Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power /clock distribution, packaging, P&R and timing ... We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented...love the challenge of crafting the fastest and most power efficient chips in their class? If so, we… more
    NVIDIA (08/12/25)
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  • Hardware Engineer | Hardware Design

    Cisco (Milpitas, CA)
    Hardware Engineer | Hardware Design | Routers Apply (https://jobs.cisco.com/jobs/Login?projectId=1450983) + Location:Milpitas, California, US + Alternate ... the hardware for the 8000 series routers to deliver the best quality, best power efficiency using cutting edge series technology at the highest bit rates possible.… more
    Cisco (10/01/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion Compiler to join our ... to improve PPA + Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence...Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power more
    NVIDIA (09/09/25)
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  • Package Design Engineer

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom is seeking an experienced IC package- design engineer for complex flip-chip-BGA packages for industry-leading ASICs ... with high-speed SerDes and very-high- power delivery needs. You will be part of a...to create the package structures needed to enable new design , and contribute to efficiency improvements for our … more
    Broadcom (08/19/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our outstanding Networking Silicon ... for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, power and...Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power more
    NVIDIA (09/09/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …engineers to help achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... **Responsibilities** + Own and drive the development of microarchitecture and RTL design , coding, and verification of complex IP blocks, including: + Mixed-signal… more
    Microsoft Corporation (09/30/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …of power intent files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design , pinning and budgeting flows + ... + Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions...Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure… more
    NVIDIA (08/20/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …skill Other highly desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The candidate ... , verification, and synthesis. Must have strong UNIX-based EDA tool skills and knowledge of ASIC design flows. Must be familiar with reusable HDL coding styles… more
    Broadcom (07/26/25)
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