- Capgemini (San Francisco, CA)
- …_ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification ( DV ) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** ... **Job description:** Analog/Mixed-Signal Design Verification **Key responsibilities:** + Extract...Develop timing model for the circuit working with layout engineer . + This role will provide the ability to… more
- Cisco (San Jose, CA)
- …and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as ... ASIC in deployment-mode applications * You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the… more
- Amazon (San Diego, CA)
- …technologies. In this role you will: . Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models . ... be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness ....blocks to ensure functional correctness . Work with the design and communication systems team and participate in system… more
- Qualcomm (San Diego, CA)
- …physical design (PD) team for physical implementation of the IPs - Work with design verification ( DV ) team to define test plans, verify the design ... C) for improving productivity and efficiency - Experience supporting mixed-signal design verification **Minimum Qualifications:** * Bachelor's degree in Science,… more
- Amazon (Cupertino, CA)
- …design from micro-architecture through physical design - Good knowledge of design verification ( DV ) simulation methodologies - Experience with large ... Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers....cost effective DFT methodologies * Perform RTL coding and Verification * Participate in Silicon debug and write scripts… more
- Micron Technology, Inc. (San Jose, CA)
- …models (LLMs) for the purpose of automated Silicon design and Design Verification ( DV ). The engineer is expected to build LLM based EDA workflows ... which assists the Design Engineers in building the next Micron product at higher velocity and greater quality. **Responsibilities:** + Optimize and fine-tune… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins Champion the customer needs ... Experience in writing scripts (Perl, Python or Tcl) Strong software, HDL design and verification skills Experience with SystemVerilog, VHDL, Verilog,… more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects ... Plans and Testbenches for your functional domain. + Execute Verification Plans, including Design Bring-up, DV...correctness. + Experience in leading a small team of Verification engineers performing CPU Verification .… more
- Qualcomm (Santa Clara, CA)
- …As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a ... a team defining the processes, methods and tools for design verification of large complex IP blocks...+ Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV… more
- BAE Systems (San Diego, CA)
- …your skills, and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop ... your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP...be available based on position level and/or job specifics. ** Design Verification Engineer - FPGA… more