• Senior E/E & Semiconductor Engineer

    Capgemini (San Jose, CA)
    …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** ... **Job Role: Senior** **Mixed Signal DV Engineer ** **Job Location: San Jose...This role will provide the ability to directly influence design related changes as required to meet functional specifications.… more
    Capgemini (03/19/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will ... towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1....7. Experience in verifying a IP block using standard DV based techniques. 8. Experience in EDA tools and… more
    Meta (02/12/25)
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  • Senior Design Verification

    BAE Systems (San Diego, CA)
    …growing your skills, and advancing your career. BAE is looking for experienced FPGA Design Verification Engineers who can develop and use verification ... evolution of our processes and methodologies. + Enhance your DV skills as well as your knowledge of Electronic...available based on position level and/or job specifics. **Senior Design Verification Engineer - FPGA**… more
    BAE Systems (02/21/25)
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  • ASICS Design Verification

    Qualcomm (Santa Clara, CA)
    …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... flow and methodology. Involve in developing automation to improve verification efficiency. **Qualifications:** + DV experience using uvm/assertion based… more
    Qualcomm (03/07/25)
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  • FPGA Verification Engineer , Kuiper…

    Amazon (Sunnyvale, CA)
    …to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to ... Enhance your leadership skills while contributing to a dynamic DV team * Create reusable Verification IP...verification simulation solutions. The FPGA verification engineer will work with FPGA design and… more
    Amazon (04/05/25)
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  • Senior ASIC Design Verification

    Cisco (San Jose, CA)
    …, and post-silicon validation The team comprises micro-architects, front-end designers, and verification engineers . Cisco is a system company, so you can ... shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation models, test… more
    Cisco (03/05/25)
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  • SOC Verification and Methodology…

    Qualcomm (San Diego, CA)
    …transformation to help create a smarter, connected future for all. We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and ... resolve design issues. In this role of Design Verification Engineer , you will...verification challenges with minimal guidance. Ramp-up on new verification tools and methodologies. Explore innovative DV more
    Qualcomm (04/18/25)
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  • SOC Verification and Methodology…

    Qualcomm (San Diego, CA)
    …the Invention Age - and this is where you come in. We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification ... resolve design issues. In this role of Design Verification Engineer , you will...verification challenges with minimal guidance. Ramp-up on new verification tools and methodologies. Explore innovative DV more
    Qualcomm (02/12/25)
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  • ASIC Verification Engineer

    Cisco (San Jose, CA)
    …of the most complex ASICs being developed in the industry. Your Impact As ASIC Verification Engineer in The Core Hardware Business Unit, you will be engaged the ... infrastructure for block, cluster and top level environments. *Maintaining existing DV environments and enhancing them *Ensuring complete verification coverage… more
    Cisco (04/25/25)
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  • ASIC Verification Engineer

    Cisco (San Jose, CA)
    …with focus on reuse. * Defining new DV methodologies. * End-to-end verification of one or more design blocks simultaneously while helping the full ... will engage in dynamic collaboration with Senior micro-architects, designers, and verification engineers and interact with cross-functional software and product… more
    Cisco (04/25/25)
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