- Google (Sunnyvale, CA)
- …about benefits at Google (https://careers.google.com/benefits/) . **Responsibilities:** + Define and develop Field - Programmable Gate Array (FPGA) based ... + PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field , or equivalent practical experience. + 4 years of experience working in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
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