• Display Driver Engineer

    Meta (Sunnyvale, CA)
    …pipeline for Displays and DDIC/Display Driver Integrated Circuit architecture 11. Experience with FPGA/ Field - Programmable Gate Array prototyping 12. 5+ ... the algorithms 2. Collaborate with DDIC architects to optimize algorithms for optimal gate -count and timing 3. Collaborate with the optics and visual quality teams… more
    Meta (06/25/25)
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  • Silicon Validation Engineer

    Google (Mountain View, CA)
    …interface with excellent debugging skills. + Experience executing tests on emulation platforms or Field - programmable Gate Array (FPGA). + Experience with ... Electrical Engineering, Computer Engineering, Computer Science, or a related field , or equivalent practical experience. + 3 years of...to create test plans. + Support silicon debug and field failures. Google is proud to be an equal… more
    Google (06/21/25)
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  • Senior Silicon Digital Design Engineer

    Google (Mountain View, CA)
    …these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset. + Knowledge of Field Programmable Gate Array (FPGA) and ... degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field , or equivalent practical experience. + 5 years of experience with… more
    Google (05/23/25)
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  • Principal FPGA Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
    Cadence Design Systems, Inc. (05/06/25)
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  • Principal FPGA Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
    Cadence Design Systems, Inc. (04/09/25)
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