• CPU Verification DevOps Engineer

    Google (Mountain View, CA)
    …Verification team. + Develop and manage large-scale regression flows for simulation, emulation, field - programmable gate array (FPGA) platforms, including ... degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field , or equivalent practical experience. + 3 years of Experience with… more
    Google (03/25/25)
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  • Senior FPGA Verification Engineer

    Jet Propulsion Laboratory (Pasadena, CA)
    …the Group Supervisor of the **Radar Digital Electronics Group** . We are seeking a ** Field Programmable Gate Array (FPGA) Verification Engineer IV** , ... Tracking, and Radar Division conducts research, development, and flight missions in the field of airborne and spaceborne remote sensing radar for NASA and other… more
    Jet Propulsion Laboratory (02/06/25)
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  • Senior FPGA Design Engineer

    Jet Propulsion Laboratory (Pasadena, CA)
    …and the Group Supervisor of the **Radar Digital Systems Group** . We are seeking a ** Field Programmable Gate Array (FPGA) Engineer IV** , responsible for ... Tracking, and Radar Division conducts research, development, and flight missions in the field of airborne and spaceborne remote sensing radar for NASA and other… more
    Jet Propulsion Laboratory (02/05/25)
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  • Lead or Senior FPGA Design Engineer

    The Boeing Company (Huntington Beach, CA)
    …for professional growth. Find your future with us. We are seeking a **Lead or Senior** ** Field Programmable Gate Array (FPGA) Design Engineer** to join ... our team in **Huntington Beach, California** with experience in the development of mission systems for space and airborne platforms to support and lead development of next generation electronics for optical sensing systems from conceptual design through… more
    The Boeing Company (05/03/25)
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  • Principal FPGA Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
    Cadence Design Systems, Inc. (04/09/25)
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  • Principal FPGA Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …verification, timing closure and hardware validation of the FPGA IPs. + Developing field - programmable gate array intellectual properties (FPGA IPs) ... for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; + Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; + Enhancing current IPs… more
    Cadence Design Systems, Inc. (02/04/25)
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