• ASIC Engineer, Formal Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal ... to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the… more
    Meta (12/20/25)
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  • Design Verification Engineer

    Arrow Electronics (Austin, TX)
    …functional and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification ... **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC SoC… more
    Arrow Electronics (12/25/25)
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  • Sr. ASIC Design Verification Engineer…

    Amazon (Austin, TX)
    …. Participate in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
    Amazon (12/13/25)
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  • Principal SoC Design Verification Engineer

    Global Foundries (Richardson, TX)
    …Background with pow er-aware (UPF) and gate-level simulations (GLS) + Familiarity of formal verification tools and techniques . Expected Salary Range $94,300.00 ... visit www.gf.com. Summary of Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Data Processing Unit Chiplets and… more
    Global Foundries (12/12/25)
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  • MLA IP Design Verification Engineer,…

    Amazon (Austin, TX)
    …Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - ... in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our… more
    Amazon (11/27/25)
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  • Design Verification Engineer, Annapurna ML

    Amazon (Austin, TX)
    …Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - ... solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our… more
    Amazon (01/01/26)
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  • ASIC Engineer, SoC Verification

    Meta (Austin, TX)
    …Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in EDA tools and scripting ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
    Meta (12/20/25)
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  • ASIC Engineer, Design Verification

    Meta (Austin, TX)
    …13. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14. Experience in development of UVM ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
    Meta (12/20/25)
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  • ASIC Engineer, Performance & Package…

    Meta (Austin, TX)
    …Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in EDA tools and scripting ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
    Meta (12/20/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off - Develop physical design methodologies -… more
    Amazon (12/02/25)
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