• Computer Architect/Embedded Computing Systems…

    The Boeing Company (El Segundo, CA)
    …& Weapons Systems has an exciting opportunity for a **Computer Architect/Embedded Computing Systems Design Engineer (Lead or Senior)** to join us as part of our ... SI&WS Electronics design team located in **El Segundo, CA.** If you...have an exciting opportunity for you. As a Computer Engineer Architect on our SI&WS Electronics team at Boeing… more
    The Boeing Company (10/08/25)
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  • Senior FPGA / Rtl Design Engineer

    Silvus Technologies (Los Angeles, CA)
    …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
    Silvus Technologies (10/08/25)
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  • Senior Digital Design Engineer

    NVIDIA (Santa Clara, CA)
    …System Verilog, logic design concepts, and typical structures. + Good understanding of design for test, timing constraints, and static timing analysis. + ... be translated into RTL and firmware designs. For backend design , you will define, build synthesis constraints and drive..., you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and… more
    NVIDIA (09/26/25)
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  • Staff Silicon Design Engineer

    Google (Fremont, CA)
    Staff Silicon Design Engineer , Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... Verilog or SystemVerilog. + Experience of synthesis and static timing analysis. + Experience in silicon validation of ASICs,...Raxium is seeking a highly motivated and skilled Digital Design Engineer with expertise in SystemVerilog to… more
    Google (10/07/25)
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  • ASIC and/or FPGA Design & Verification…

    The Boeing Company (Huntington Beach, CA)
    … practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part… more
    The Boeing Company (10/04/25)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
    Silvus Technologies (08/18/25)
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  • Sr. RTL Design Engineer , Hardware…

    Amazon (Sunnyvale, CA)
    …TV and Amazon Echo. What will you help us create? The Role: As a Senior RTL Design Engineer , you will be part of an advanced architecture team that is exploring ... methodologies and EDA tools - Experience working with Synthesis, timing closure, and design constraints - Excellent...domains - Large breadth of knowledge from architecture through physical design - Knowledge of FPGA and… more
    Amazon (10/05/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Circuit Design Engineer ! NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 ... for hardware security, adaptive clocking, and power management solutions. + Drive the design and physical implementation of custom digital IPs from RTL to… more
    NVIDIA (09/03/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …involve in engineering implementation spec writing from marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will ... team. You will work closely with marketing, architecture, firmware, physical and layout teams on full product development cycle...either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years… more
    Broadcom (07/26/25)
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  • Senior Engineer - Design for Test…

    Microsoft Corporation (Mountain View, CA)
    …highly energetic cross functional team members (Architects, front-end & back-end design /verification, Physical design , and post-silicon manufacturing) with ... the Cloud infrastructure. We are looking for a **Senior Design for Test (DFT) Engineer ** to join...for achieving high fault coverage. + Experience with Static Timing Analysis & constraint generation. + Experience with ATE… more
    Microsoft Corporation (10/09/25)
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