- NVIDIA (Westford, MA)
- …a significant impact! What you'll be doing: + Run integration flows to build RTL , run connectivity checks, and assemble logical units. + Perform linting checks and ... debug RTL and netlist-level issues. + Collaborate with front-end teams...connectivity issues and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows.… more
- Cisco (Maynard, MA)
- …to FPGA Emulation of ASIC Blocks** + **Contribute to our custom ASIC RTL code** **Minimum Qualifications:** + **Bachelors +8 years of experience, or Masters +6 ... FPGA design and verification experience** + **Experience in Verilog RTL coding and synthesis for FPGAs** + **Experience with...FPGAs** + **Expertise in creating FPGA implementations from ASIC RTL code** + **Expertise in digital design of standard… more
- Cisco (Maynard, MA)
- …networks. This role sits on our ASIC team providing infrastructure support for RTL implementation to gates. **Your Impact** You will collaborate with Acacia's ASIC ... to deliver tape-out quality physical designs. You will work closely with RTL designers to debug and root-cause physical implementation issues related to design,… more
- Amazon (North Reading, MA)
- …early in design cycle -Execute on design specifications to deliver high quality RTL -Ensure quality by running and tracking results of front-end tools including: ... Synthesis, Lint ( RTL , DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage -Work with pre-silicon… more
- Actalent (North Reading, MA)
- …Engineering, or related field. + Professional experience in FPGA development: RTL design, verification, timing analysis, lab bring-up, and validation. + Proficiency ... in Verilog and digital design principles. + Strong understanding of DSP fundamentals and their implementation on FPGAs. + Familiarity with computing and processor architectures. + Experience with simulation and verification tools. + Excellent problem-solving… more
- NVIDIA (Westford, MA)
- …targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, ... timing and power convergence, and ECO implementation. What we need to see: + Great teammate + BS (or equivalent experience) in Electrical or Computer Engineering + 8+ years experience or MS (or equivalent experience) with 2 years experience in Synthesis and… more
- NVIDIA (Westford, MA)
- …+ Participating in microarchitecture development and document specifications. + Implementing in RTL and debug working with the verification team to ensure that the ... design is functional and performant. + Applying logic design skills to optimize and meet performance and power goals. + Delivering a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable… more
- CDM Smith (Boston, MA)
- **42082BR** **Requisition ID:** 42082BR **Business Unit:** TSU **Job Description:** Essential RTL Job Functions: - Provide strong leadership to help drive a strong ... culture and foster engagement while supporting the firm's vision framework. - Recruit, interview, and hire new employees to support project workload and overall firm growth. - Retain our best and brightest and support your employees' career journey. - Actively… more
- Draper (Boston, MA)
- …buses + Work in both block-level/chip-level UVM testbench environment + Work with RTL designers to resolve simulation issues + Implement cover groups according to ... design requirements + Work on code and functional coverage closures to achieve 100% + Perform code reviews and to mentor junior engineers in the group + Fluent in System Verilog including SVA + Recent experience with UVM/UVMF + Familiarity with at least one… more
- Draper (Boston, MA)
- …buses + Work in both block-level/chip-level UVM testbench environment + Work with RTL designers to resolve simulation issues + Implement cover groups according to ... design requirements + Work on code and functional coverage closures to achieve 100% + Perform code reviews and to mentor junior engineers in the group + Fluent in System Verilog including SVA + Recent experience with UVM/UVMF + Familiarity with at least one… more