• Principal / Senior Principal FPGA

    Northrop Grumman (Annapolis Junction, MD)
    …in HDL (VHDL/Verilog) and HVL (SystemVerilog) + Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology (UVM) + Experience with ... in HDL (VHDL/Verilog) and HVL (SystemVerilog) + Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology (UVM) + Experience with… more
    Northrop Grumman (08/08/25)
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  • Staff Lead Design Verification Engineer

    Northrop Grumman (Annapolis Junction, MD)
    …seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will play a critical role ... Verification :** + Conduct in-depth behavioral simulations across ASIC and FPGA + Generate and execute...Identify and resolve signal delay and performance issues in gate timing requirements + Develop comprehensive Universal Verification more
    Northrop Grumman (07/18/25)
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  • Principal Digital Verification Engineer/…

    Northrop Grumman (Linthicum Heights, MD)
    …team in Mission Systems that encompasses Digital Verification Engineering to support ASIC and FPGA product development. + Work closely with design and ... you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification ...I/O interfaces + Experience with SystemVerilog Assertions (SVA) + FPGA / ASIC design and/or development process experience +… more
    Northrop Grumman (05/21/25)
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  • Senior Digital Verification Engineer…

    Huntington Ingalls Industries (Fort Meade, MD)
    …thinkers who can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs. Candidates ... etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface,...Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
    Huntington Ingalls Industries (07/10/25)
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  • Senior Test and Integration Engineer

    Leidos (Linthicum, MD)
    …and testing of new ASIC designs prior to fabrication using Field Programmable Gate Arrays ( FPGA ) to emulate the chips. + (U//FOUO) Write custom interfaces ... the system design, requirements, and standards. Perform in-depth security verification testing of cryptographic product designs and equipment. **CLEARANCE REQUIRED**… more
    Leidos (08/08/25)
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