- Broadcom (San Jose, CA)
- …and memory. + ARM-based SoC Architecture: Define and drive the top - level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, ... and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). + Detailed Chip Specification: Create and maintain… more
- SpaceX (Sunnyvale, CA)
- …performance and capabilities of the Starlink network. RESPONSIBILITIES: + Perform SOC top level physical design ; floor-planning, I/O, bump & RDL ... SKILLS AND EXPERIENCE: + Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard… more
- Meta (San Diego, CA)
- …7+ years of experience as a Digital Design Engineer 9. Experience with top level integration using automation tools. 10. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 11. Experience in digital design … more
- Meta (Sunnyvale, CA)
- …systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture definition and RTL ... implementation 2. Contribute to chip- level integration, verification plan development and verification 3. Define... Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration 10. Experience in digital design … more
- NVIDIA (Santa Clara, CA)
- …is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. + Zebu emulation experience with ... Testbenches). + Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test fails and emulator environment issues. + Bring-up and verify High Speed… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. + Candidates will be working ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Amazon (Sunnyvale, CA)
- …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Knowledge of ... help us create? The Role: As a Senior ASIC Design Engineer, you will be part of an advanced...image processing pipelines. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,… more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... - BS in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years of VLSI engineering - 5+ years with code quality tools… more
- NVIDIA (Santa Clara, CA)
- …Ways to stand out from the crowd: + Experience with clocks controller, clocks logic design + Understanding of system level artifacts like power, noise, etc + ... us today. The clocks group is looking for a top -notch ASIC engineer to join the team. The Team...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
- SpaceX (Irvine, CA)
- …+ Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean ... Pay range: ASIC Design Engineer/Senior: $160,000.00 - $220,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may… more