- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... - BS in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years in VLSI engineering - 5+ years with code quality tools… more
- Arrow Electronics (San Jose, CA)
- …and supporting our prototyping methodology. + **Option to engage in block- level RTL design or block or top - level IP integration.** + Collaborate with ... **What candidate will Be Doing:** + Map multi-million gate SoC designs onto prototyping platforms, creating design ...based upon geographic location, work experience, education, and/or skill level . The pay ratio between base pay and target… more
- Cisco (San Jose, CA)
- …provide solutions and ensure signoff clean results. + Work closely with block and TOP level physical implementation, IP development teams and to resolve PV ... robustness. + Guide and mentor a team of physical design engineers on project- level backend implementation and...with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical … more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC...salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top -notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get… more
- Meta (Sunnyvale, CA)
- …Define and track detailed test plans for the different modules and top level systems. Validation coverage includes SoC , low speed signal interface (I2C, I2S, ... **Summary:** Electrical Design Validation Engineer in Wearables Hardware will be...Python, and LabVIEW development experience 18. Board and system level validation and debugging experience 19. Experience with mobile… more
- Cisco (San Jose, CA)
- …System Verilog and UVM methodology + Prior experience in verifying complex blocks, clusters and top level for SoC + Prior experience building test benches ... ASIC Design Verification Engineer, Technical Leader Apply (https://jobs.cisco.com/jobs/Login?projectId=1447177) +...that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. + Candidates will be working ... Testbenches). + Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test fails and emulator environment issues. + Bring-up and verify High Speed… more
- NVIDIA (Santa Clara, CA)
- …with memory systems in the lab. + You have working experience in taking an SOC from concept level to production. + Detailed understanding of DRAM, DRAM ... a Lead DRAM Memory Subsystem Validation Engineer within the GPU/ SOC Engineering Team to help drive development of future...+ In Pre-Silicon phase, ability to work with the design and verification teams to define features required for… more
- Meta (Sunnyvale, CA)
- …1. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... teams and vendors **Preferred Qualifications:** Preferred Qualifications: 14. Experience with SOC Design Integration & Front End Implementation 15. Experience… more