- ManpowerGroup (Folsom, CA)
- …with a 12 month project to start plus extensions. We are seeking an experienced System -on- Chip (SoC) Performance Modeling Engineer to join our team. The ... Experis is seeking a SoC Performance Modeling Engineer for a high tech client in Folsom,...have a strong background in performance modeling of memory systems using C++, as well as experience in trace… more
- Google (Mountain View, CA)
- …you'll have the opportunity to revolutionise AI by applying state-of-the-art AI to Chip Design. We develop research breakthroughs that impact all aspects of the ... develop and apply state-of-the-art AI methods and models to Chip Design and work closely with research and product...ML models, hardware generation and verification, RTL optimization, and system design. + Engage and work in a fast… more
- Skyworks (San Jose, CA)
- …for the fast-paced and highly competitive cellular handset market. + As a Multi- Chip Module Design Engineer , you will be responsible for developing ... RF Module Engineer - Summer/Fall Co-Op Apply now " Date:Aug...concept to final production, whether your specialty is in multi- chip modules, power amplifiers, RFICs or PMICs, RF filters,… more
- Meta (Sunnyvale, CA)
- …mix and match the real and virtual worlds throughout the day.As an Analog Mixed Signal Chip Application Engineer at Meta, you will work with a group of engineers ... ways to map the human body. We work across the entire stack of system design, from transistors, architectures, firmware, and algorithms. Our chips will enable AR and… more
- Meta (Sunnyvale, CA)
- …Skills:** Silicon Validation Engineer , Reality Labs Responsibilities: 1. Responsible for System on Chip and end-to-end system validation plan ... Work with cross-functional teams (ie, architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip , and product engineer teams) to… more
- Google (Sunnyvale, CA)
- …with Signal and Power Integrity (SI/PI) analysis and design for high-speed digital systems , including chip -package co-design concepts. + Experience with SIPI or ... delivering unparalleled performance, efficiency, and integration. As a Signal Integrity/Power Integrity Engineer , you will lead chip and package design, ensuring… more
- Meta (Menlo Park, CA)
- …as part of a world-class engineering team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip -package- system co-design by driving ... includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements… more
- NVIDIA (Santa Clara, CA)
- …What you will be doing: + Lead the implementation of automated planning systems (Anaplan and Ops Data Platform), driving process standardization and team efficiency. ... our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology leadership, we want to hear from… more
- Meta (Sunnyvale, CA)
- …as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer Responsibilities: 1. Drive chip -package- system co-design optimization ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the… more
- Microsoft Corporation (Santa Clara, CA)
- …of platforms for Azure Datacenters based on our highly programmable data processing chip (DPU). As a Hardware Diagnostics Engineer , you will be responsible ... to validate all the components of the DPU based systems . **Responsibilities** + Develop test plans to validate new...and debugging tools to validate the functionality of hardware systems . + Perform product validation and verification of … more