- Power Integrations (San Jose, CA)
- Job Description: The Senior Failure Analysis Engineer will perform power supply or system level failure analysis to support RMA and internal/external customer ... will be given special consideration. + Ability to interpret system level schematics, the IC level schematics, and IC...and the ability to apply fault isolation techniques at chip level as well as PCB at power supply… more
- Amazon (San Diego, CA)
- …blocks to ensure functional correctness . Work with the design and communication systems team and participate in system level verification using test benches ... Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites...experience - 7+ years in verification preferably in communication systems - 3+ years in UVM, C, System… more
- Microsoft Corporation (Santa Clara, CA)
- …software and hardware expertise to create a highly programmable and high-performance chip with the capability to efficiently handle large data volumes. Thanks to ... the DPU's compute, storage, and networking capabilities. As a **Senior Software Engineer - Networking Control Plane** in the DPU Networking software team, you… more
- Google (Sunnyvale, CA)
- …from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, ... on and is growing every day. As a software engineer , you will work on a specific project critical...develop tools to update and debug ASIC firmware. Enable chip bring-up and hardware debugging. + Build functional or… more
- Microsoft Corporation (Mountain View, CA)
- …in an extremely efficient manner. We are looking for a **Principal Validation Engineer to join our team!** Microsoft's mission is to empower every person and ... principles, including: + Broad understanding of SoC subsystem, SoC system level, and platform level functionality + Writing scripts/software...+ Hands on expertise debugging silicon failures using on chip debug features (eg, trace or JTAG) as well… more
- Meta (Sunnyvale, CA)
- …work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. ... EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT strategies for data center… more
- Microsoft Corporation (Santa Clara, CA)
- …software and hardware expertise to create a highly programmable and high-performance chip with the capability to efficiently handle large data volumes. Thanks to ... the DPU's compute, storage, and networking capabilities. As a Principal Software Engineer in the DPU Networking software team, you will design, develop, deploy… more
- NVIDIA (Santa Clara, CA)
- …sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their ... substrate breakout patterns for ASIC packages. + Optimize package pinout incorporating system level trade-offs of pins assignment. + Help perform package routing,… more
- The Walt Disney Company (Santa Monica, CA)
- …microservices, and data visualization. We are currently seeking a **Lead Software Engineer ** to join our team. The ideal candidate will have extensive experience ... the use of design patterns, CI/CD, code review and automated test + Chip in ground-breaking innovation and apply the state-of-the-art technologies + As a key… more
- The Walt Disney Company (Glendale, CA)
- …microservices, and data visualization. We are currently seeking a **Senior Software Engineer ** to join our team. The ideal candidate will have extensive experience ... the use of design patterns, CI/CD, code review and automated test + Chip in ground-breaking innovation and apply the state-of-the-art technologies + As a key… more