• FPGA Verification Engineer , Kuiper…

    Amazon (Redmond, WA)
    …networking and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating & Maintaining ...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based… more
    Amazon (07/05/25)
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  • Design Verification Engineer

    SpaceX (Redmond, WA)
    Design Verification Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...capabilities of the Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block… more
    SpaceX (05/15/25)
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  • Design Verification Engineer

    Meta (Redmond, WA)
    …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology 10. 2+ years… more
    Meta (07/12/25)
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  • Lead E/E & Semiconductor Engineer - SOC…

    Capgemini (Seattle, WA)
    **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal candidate ... flows. **Preferred Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in… more
    Capgemini (07/15/25)
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  • Design Verification Engineer

    Meta (Redmond, WA)
    …at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
    Meta (06/24/25)
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  • Design Verification Engineer

    Amazon (Redmond, WA)
    …or Ph.D degree in Electrical / Communications Engineering - 2+ years in digital verification , preferably in communication systems - Familiarity with Matlab - ... Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM , SystemC and DPI-C .… more
    Amazon (07/04/25)
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  • Senior ASIC Verification Engineer

    Amazon (Redmond, WA)
    …Master's or Ph.D degree in Electrical / Communications Engineering * 10+ years in digital verification * Hands on experience working closely with Systems team on ... * Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM , System C and DPI-C *… more
    Amazon (07/01/25)
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  • Sr. Analog/Mixed-Signal Verification

    SpaceX (Redmond, WA)
    Sr. Analog/Mixed-Signal Verification Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR. ANALOG/MIXED-SIGNAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (06/05/25)
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  • ASIC and/or FPGA Design & Verification

    The Boeing Company (Tukwila, WA)
    …Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part of our ... enable high-integrity, low SWAP-C flight computers. And we're applying the latest digital IC design processes with industry-best tools to enable applications that… more
    The Boeing Company (07/18/25)
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  • Senior Quantum Engineer - Cryo-CMOS…

    Microsoft Corporation (Redmond, WA)
    …and Low Power Verification . + Define and implement efficient UVM -based verification environments and use them to verify+test digital designs + Test plan, ... the world. We are looking for a **Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design** ....+ Knowledge of verification principles, testbenches, Universal Verification Methodology ( UVM ), and coverage. + Experience… more
    Microsoft Corporation (07/02/25)
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