• Senior System Performance and Power…

    NVIDIA (Santa Clara, CA)
    …and power based on roadmap. + Work closely with architecture, ASIC , board/platform design , software/firmware, marketing, and other cross-functional teams ... at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking...industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team.… more
    NVIDIA (03/21/25)
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  • Image Processing and Machine Learning…

    Meta (Sunnyvale, CA)
    …product requirements. **Required Skills:** Image Processing and Machine Learning Engineer (PhD) Responsibilities: 1. Develop algorithms for image processing and ... efficiently with specialized imaging hardware, optimizing for performance, energy efficiency , and scalability. 3. Run ML models, including training, optimization,… more
    Meta (03/15/25)
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  • Diagnostic Engineer Technical Leader

    Cisco (San Jose, CA)
    …part of our team. Who You Are: We are seeking a Hardware Diagnostic Engineer Tech Lead to develop and optimize hardware diagnostic utilities for complex systems, ... for pre-production validation, manufacturing testing, and field troubleshooting. * Design and optimize firmware/software solutions for diagnosing CPU, memory,… more
    Cisco (04/17/25)
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  • Lead Test Security Engineer , Silicon

    Google (San Diego, CA)
    …unparalleled performance, efficiency , and integration. As a Lead Test Security Engineer , you will help integrate SOC technologies into mobile phones, tablets and ... respect to Test and Product Engineering activities. You will work with ASIC architecture, design , pre-silicon SOC verification to implement secure end-to-end… more
    Google (05/08/25)
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  • Test Security Engineer , Silicon

    Google (Mountain View, CA)
    …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Test Security Engineer , you will ... to Test and Product Engineering activities. you will work with ASIC Architecture, Design , Pre-silicon SOC Verification to implement secure end to end… more
    Google (05/04/25)
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  • Senior Software/Build Engineer

    Microsoft Corporation (Santa Clara, CA)
    …globalization, and manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and partners worldwide ... software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to… more
    Microsoft Corporation (04/30/25)
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  • Senior Software Engineer

    Microsoft Corporation (Mountain View, CA)
    …globalization, and manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and partners worldwide ... software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to… more
    Microsoft Corporation (05/15/25)
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  • Sr Product Test Development Engineer

    Cisco (San Jose, CA)
    …are received. Meet the Team As part of the team you will collaborate with ASIC design teams in the Central Hardware Group, peer Test and Product Engineers ... Impact You will be a Sr Product Test Development Engineer in Silicon Operations focusing on the ATE test...to production. Apply sophisticated data analytics to optimize test efficiency and drive yield improvements. Collaborate with Design… more
    Cisco (05/01/25)
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  • Physical Verification and Convergence…

    Google (Sunnyvale, CA)
    …a related field, or equivalent practical experience. + 3 years of experience in ASIC physical design flows with emphasis on physical verification convergence and ... field, or equivalent practical experience. + 3 years of experience in physical design , verification, and various methodologies. + Experience in Python, Tcl, or Perl… more
    Google (04/17/25)
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  • IC Verification Engineer

    Broadcom (San Jose, CA)
    …plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design /architecture. Driver Verification quality and Efficiency improvements ... Functional coverage and pseudo-random testing . Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on… more
    Broadcom (05/16/25)
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